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Dear Async Colleagues,
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<div class="">Two postdoctoral researcher positions are available in <a href="http://andreoulab.net/" class="">Andreas Andreou’s group</a> (JHU) and <a href="https://web.stanford.edu/group/brainsinsilicon/index.html" class="">Kwabena Boahen’s group</a> (Stanford).
We appreciate your help in getting the word out.</div>
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<div class="">Our Northrop Grumman-led team is designing a 3D-<font color="#000000" class=""><span class="">integrated imager-processor system, funded by</span></font> DARPA’s <a href="https://www.militaryaerospace.com/sensors/article/14184786/electrooptical-sensors-machine-learning" class="">FENCE</a> program<span class="" style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">.
Imager pixels and processor cores are on separate chips. These two chips are stacked with a through-silicon-via (TSV) for each </span><span class="" style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">pixel</span> <span class="" style="caret-color: rgb(0, 0, 0); color: rgb(0, 0, 0);">signal.
A</span><font color="#000000" class=""> bit-serial NoC routes pixel-produced events to cores. A bit-parallel NoC routes data between cores. Both NoCs are asynchronous. </font></div>
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<div class=""><font color="#000000" class=""><span class="">This</span> project builds on work our groups published on </font><a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7028244" class="">3D imager-processor integration</a><font color="#000000" class="">, </font><font color="#000000" class="">a </font><a href="https://web.stanford.edu/group/brainsinsilicon/documents/MerollaEtAlRouterFinal.pdf" class="">bit-parallel
interchip network</a><font color="#000000" class="">, and </font><font color="#000000" class="">a </font><a href="https://web.stanford.edu/group/brainsinsilicon/documents/serial-h-tree.pdf" class="">bit-serial NoC</a><font color="#000000" class="">. </font><span class="" style="color: rgb(0, 0, 0);"> </span></div>
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<div class=""><font color="#000000" class="">The ideal candidate should <span style="caret-color: rgb(0, 0, 0);" class="">have</span> a PhD in EE or CS, and experience designing, taping out, and characterizing an asynchronous system-on-chip. Previous experience
in event-based imaging and/or processing is preferred but not required. The position would ideally start as soon as possible (Summer 2021). </font></div>
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<div class=""><font color="#000000" class="">To apply, please send a CV, a research statement, and contact information for three references to
</font><a href="mailto:andreou@jhu.edu" class="">andreou@jhu.edu</a><font color="#000000" class=""> and </font><a href="mailto:boahen@stanford.edu" class="">boahen@stanford.edu</a><font color="#000000" class="">, with the subject “FENCE Postdoc Application”.
Applications will be reviewed on a rolling basis until the position is filled. </font></div>
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Warmest regards<br class="">
Kwabena Boahen (and Andreas Andreou)<br class="">
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Director, <a href="https://web.stanford.edu/group/brainsinsilicon/" class="">Brains in Silicon</a> Lab<br class="">
Investigator, Bio-X Institute and Wu Tsai Neurosciences Institute<br class="">
Professor, Bioengineering, Electrical Engineering and, by courtesy, Computer Science</div>
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Stanford University Schools of Medicine and Engineering</div>
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650 724 5633 (W) / 650 787 5966 (C)</div>
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<a href="https://engineering.stanford.edu/magazine/article/kwabena-boahen-how-build-super-efficient-super-computer" class="">How to build a super-efficient super-computer</a> [25 min interview]<br class="">
<a href="https://www.youtube.com/watch?v=cYpr0xzNuLk" class="">The Future of Computing: 3D Silicon Brains</a> [20 min talk]<br class="">
<a href="https://www.youtube.com/watch?v=lVQnsDSBpjI" class="">Brain-Like Computer Chips for AI</a> [1 hr talk]</div>
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